# Generated by abuild 3.18.0_rc3-r1
# using fakeroot version 1.37.2
pkgname = verilator
pkgver = 5.050-r1
pkgdesc = Convert Verilog and SystemVerilog to C++ or SystemC
url = https://verilator.org
builddate = 1784760087
packager = Buildozer <alpine-devel@lists.alpinelinux.org>
size = 33391805
arch = riscv64
origin = verilator
commit = eceb05f7d2e0e3a3dbb76cd8b196855d880046d7
license = LGPL-3.0-only
depend = perl
# automatically detected:
provides = cmd:verilator=5.050-r1
provides = cmd:verilator_bin=5.050-r1
provides = cmd:verilator_bin_dbg=5.050-r1
provides = cmd:verilator_coverage=5.050-r1
provides = cmd:verilator_coverage_bin_dbg=5.050-r1
provides = cmd:verilator_gantt=5.050-r1
provides = cmd:verilator_profcfunc=5.050-r1
depend = so:libc.musl-riscv64.so.1
datahash = 378ef58c4e8b2c4e113e2b7d77301bc1cbc6969ef990aedb80bffc62ea2e150f
